Cypress Semiconductor CY7C1334H Технічна специфікація - Сторінка 9

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Switching Characteristics

Parameter
t
V
(typical) to the First Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid after CLK Rise
CO
t
Data Output Hold after CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
t
OE LOW to Output Valid
OEV
t
OE LOW to Output Low-Z
OELZ
t
OE HIGH to Output High-Z
OEHZ
Set-up Times
t
Address Set-up before CLK Rise
AS
t
ADV/LD Set-up before CLK Rise
ALS
t
GW, BW
WES
t
CEN Set-up before CLK Rise
CENS
t
Data Input Set-up before CLK Rise
DS
t
Chip Enable Set-Up before CLK Rise
CES
Hold Times
t
Address Hold after CLK Rise
AH
t
ADV/LD Hold after CLK Rise
ALH
t
GW, BW
WEH
t
CEN Hold after CLK Rise
CENH
t
Data Input Hold after CLK Rise
DH
t
Chip Enable Hold after CLK Rise
CEH
Notes:
12. Test conditions shown in (a), (b) and (c) of AC Test Loads.
13. Timing reference level is 1.5V when V
14. This part has a voltage regulator internally; t
can be initiated.
15. t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
16. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve Tri-State prior to Low-Z under the same system conditions
17. This parameter is sampled and not 100% tested.
Document #: 38-05678 Rev. *B
Over the Operating Range
Description
[14]
[15, 16, 17]
[15, 16, 17]
[15, 16, 17]
[15, 16, 17]
Set-up before CLK Rise
[A:D]
Hold after CLK Rise
[A:D]
= 3.3V and 1.25V when V
DDQ
DDQ
is the time that the power needs to be supplied above V
POWER
is less than t
and t
OEHZ
OELZ
CHZ
[12, 13]
166 MHz
Min.
1
6.0
2.5
2.5
1.5
0
0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
= 2.5V.
minimum initially before a Read or Write operation
DD
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
CY7C1334H
133 MHz
Max.
Min.
Max.
1
7.5
3.0
3.0
3.5
4.0
1.5
0
3.5
4.0
3.5
4.0
0
3.5
4.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Page 9 of 13
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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