Cypress Semiconductor CY7C1353G Технічна специфікація - Сторінка 4

Переглянути онлайн або завантажити pdf Технічна специфікація для Комп'ютерне обладнання Cypress Semiconductor CY7C1353G. Cypress Semiconductor CY7C1353G 14 сторінок. Cypress 4-mbit (256k x 18) flow-through sram with nobl architecture specification sheet

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Functional Overview

The CY7C1353G is a synchronous flow-through burst SRAM

designed specifically to eliminate wait states during

Write-Read transitions. All synchronous inputs pass through

input registers controlled by the rising edge of the clock. The

clock signal is qualified with the Clock Enable input signal

(CEN). If CEN is HIGH, the clock signal is not recognized and

all internal states are maintained. All synchronous operations

are qualified with CEN. Maximum access delay from the clock

rise (t

) is 6.5 ns (133-MHz device).

CDV

Accesses can be initiated by asserting all three Chip Enables

(CE

, CE

) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device is latched. The access

can either be a read or write operation, depending on the

status of the Write Enable (WE). BW

conduct byte write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self timed write

circuitry.

Three synchronous Chip Enables (CE

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipe lined.

ADV/LD must be driven LOW after the device has been

deselected to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

and CE

are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and 4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory array

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the output buffers. The data is available within 6.5

ns (133-MHz device) provided OE is active LOW. After the first

clock of the read access, the output buffers are controlled by

OE and the internal control logic. OE must be driven LOW in

order for the device to drive out the requested data. On the

subsequent clock, another operation (Read/Write/Deselect)

can be initiated. When the SRAM is deselected at clock rise

by one of the chip enable signals, its output is tri-stated

immediately.

Burst Read Accesses

The CY7C1353G has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Reads without reasserting the address inputs. ADV/LD

must be driven LOW to load a new address into the SRAM, as

described in the Single Read Access section. The sequence

of the burst counter is determined by the MODE input signal.

A LOW input on MODE selects a linear burst mode, a HIGH

selects an interleaved burst sequence. Both burst counters

use A0 and A1 in the burst sequence, and wraps around when

incremented sufficiently. A HIGH input on ADV/LD increments

the internal burst counter regardless of the state of chip enable

inputs or WE. WE is latched at the beginning of a burst cycle.

Document #: 38-05515 Rev. *E

Therefore, the type of access (Read or Write) is maintained

throughout the burst sequence.

Single Write Accesses

Write access are initiated when these conditions are satisfied

at clock rise:

• CEN is asserted LOW

• CE

• The write signal WE is asserted LOW.

The address presented to the address bus is loaded into the

Address Register. The write signals are latched into the

Control Logic block. The data lines are automatically tri-stated

regardless of the state of the OE input signal. This allows the

external logic to present the data on DQs and DQP

On the next clock rise the data presented to DQs and DQP

can be used to

[A:B]

(or a subset for byte write operations, see truth table for

details) inputs is latched into the device and the write is

complete. Additional accesses (Read/Write/Deselect) can be

initiated on this cycle.

The data written during the Write operation is controlled by

, CE

) and an

capability that is described in the truth table. Asserting the

Write Enable input (WE) with the selected Byte Write Select

input selectively writes to only the desired bytes. Bytes not

selected during a byte write operation remains unaltered. A

synchronous self timed write mechanism has been provided

to simplify the write operations. Byte write capability has been

included to greatly simplify Read/Modify/Write sequences,

, CE

which can be reduced to simple byte write operations.

Because the CY7C1353G is a common IO device, data must

not be driven into the device while the outputs are active. The

Output Enable (OE) can be deasserted HIGH before

presenting data to the DQs and DQP

tri-states the output drivers. As a safety precaution, DQs and

DQP

a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1353G has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Write operations without reasserting the address inputs.

ADV/LD must be driven LOW to load the initial address, as

described in the Single Write Access section. When ADV/LD

is driven HIGH on the subsequent clock rise, the Chip Enables

(CE

counter is incremented. The correct BW

driven in each cycle of the burst write, to write the correct bytes

of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation "sleep" mode. Two

clock cycles are required to enter into or exit from this "sleep"

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the "sleep" mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the "sleep" mode. CE

for the duration of t

, CE

, and CE

are ALL asserted active

signals. The CY7C1353G provides byte write

[A:B]

.are automatically tri-stated during the data portion of

[A:B]

, CE

, and CE

) and WE inputs are ignored and the burst

, CE

, and CE

after the ZZ input returns LOW.

ZZREC

CY7C1353G

[A:B]

inputs. Doing so

[A:B]

inputs must be

[A:B]

, must remain inactive

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