Cypress Semiconductor MoBL CY62157E Технічна специфікація - Сторінка 5

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Switching Characteristics

Parameter
Read Cycle
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE
LOW and CE
ACE
1
t
OE LOW to Data Valid
DOE
t
OE LOW to LOW Z
LZOE
t
OE HIGH to High Z
HZOE
t
CE
LOW and CE
LZCE
1
t
CE
HIGH and CE
HZCE
1
t
CE
LOW and CE
PU
1
t
CE
HIGH and CE
PD
1
t
BLE/BHE LOW to Data Valid
DBE
t
BLE/BHE LOW to Low Z
LZBE
t
BLE/BHE HIGH to HIGH Z
HZBE
[15]
Write Cycle
t
Write Cycle Time
WC
t
CE
LOW and CE
SCE
1
t
Address Set-Up to Write End
AW
t
Address Hold from Write End
HA
t
Address Set-Up to Write Start
SA
t
WE Pulse Width
PWE
t
BLE/BHE LOW to Write End
BW
t
Data Set-Up to Write End
SD
t
Data Hold from Write End
HD
t
WE LOW to High-Z
HZWE
t
WE HIGH to Low-Z
LZWE
Notes:
12. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
levels of 0 to V
, and output loading of the specified I
CC(typ)
13. At any given temperature and voltage condition, t
given device.
14. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE
HZCE
HZBE
HZWE
15. The internal Write time of the memory is defined by the overlap of WE, CE
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
Document #: 38-05695 Rev. *C
[12]
Over the Operating Range
Description
HIGH to Data Valid
2
[13]
[13, 14]
[13]
HIGH to Low Z
2
[13, 14]
LOW to High Z
2
HIGH to Power-Up
2
LOW to Power-Down
2
[13]
[13, 14]
HIGH to Write End
2
[13, 14]
[13]
/I
as shown in the "AC Test Loads and Waveforms" section.
OL
OH
is less than t
, t
HZCE
LZCE
HZBE
= V
1
45 ns
Min
Max
Min
45
45
10
45
22
5
18
10
18
0
45
45
10
18
45
35
35
0
0
35
35
25
0
18
10
is less than t
, t
is less than t
LZBE
HZOE
LZOE
, BHE and/or BLE = V
, and CE
= V
IL
IL
2
®
CY62157E MoBL
55 ns
Max
Unit
55
ns
55
ns
10
ns
55
ns
25
ns
5
ns
20
ns
10
ns
20
ns
0
ns
55
ns
55
ns
10
ns
20
ns
55
ns
40
ns
40
ns
0
ns
0
ns
40
ns
40
ns
25
ns
0
ns
20
ns
10
ns
/2, input pulse
CC(typ)
, and t
is less than t
for any
HZWE
LZWE
. All signals must be ACTIVE to initiate
IH
Page 5 of 12
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