Cypress Semiconductor NoBL CY7C1352G Технічна специфікація - Сторінка 10
Переглянути онлайн або завантажити pdf Технічна специфікація для Комп'ютерне обладнання Cypress Semiconductor NoBL CY7C1352G. Cypress Semiconductor NoBL CY7C1352G 13 сторінок. 4-mbit (256k x 18) pipelined sram with nobl architecture
Друкувати сторінкуSwitching Waveforms
NOP, STALL, and DESELECT Cycles
1
CLK
CEN
CE
ADV/LD
WE
BW
[A:B]
A1
ADDRESS
Data
In-Out (DQ)
WRITE
D(A1)
[22, 23]
ZZ Mode Timing
CLK
ZZ
I
SUPPLY
ALL INPUTS
(except ZZ)
Notes:
21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
22. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
23. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05514 Rev. *D
(continued)
[18, 19, 21]
2
3
4
A2
A3
D(A1)
READ
STALL
READ
Q(A2)
Q(A3)
DON'T CARE
t
ZZ
t
ZZI
I
DDZZ
5
6
7
A4
Q(A2)
Q(A3)
WRITE
STALL
NOP
D(A4)
UNDEFINED
t RZZI
DESELECT or READ Only
CY7C1352G
8
9
10
A5
t
CHZ
D(A4)
Q(A5)
READ
DESELECT
CONTINUE
Q(A5)
DESELECT
t
ZZREC
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