Cypress Semiconductor Perform CY62167E MoBL Посібник - Сторінка 5

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Switching Characteristics

[13, 14]
Over the Operating Range
Parameter

READ CYCLE

t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE
LOW and CE
ACE
1
t
OE LOW to Data Valid
DOE
t
OE LOW to LOW-Z
LZOE
t
OE HIGH to High-Z
HZOE
t
CE
LOW and CE
LZCE
1
t
CE
HIGH and CE
HZCE
1
t
CE
LOW and CE
PU
1
t
CE
HIGH and CE
PD
1
t
BLE/BHE LOW to Data Valid
DBE
t
BLE/BHE LOW to Low-Z
LZBE
t
BLE/BHE HIGH to HIGH-Z
HZBE
[17]
WRITE CYCLE
t
Write Cycle Time
WC
t
CE
LOW and CE
SCE
1
t
Address Setup to Write End
AW
t
Address Hold from Write End
HA
t
Address Setup to Write Start
SA
t
WE Pulse Width
PWE
t
BLE/BHE LOW to Write End
BW
t
Data Setup to Write End
SD
t
Data Hold from Write End
HD
t
WE LOW to High-Z
HZWE
t
WE HIGH to Low-Z
LZWE
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of V
of 0 to V
(typ), and output loading of the specified I
CC
14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
15. At any temperature and voltage condition, t
16. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE
HZCE
HZBE
HZWE
17. The internal write time of the memory is defined by the overlap of WE, CE
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing should be referenced to the edge of the signal that
terminates the write.
Document #: 001-15607 Rev. *A
Description
HIGH to Data Valid
2
[15]
[15, 16]
[15]
HIGH to Low-Z
2
[15, 16]
LOW to High-Z
2
HIGH to Power Up
2
LOW to Power Down
2
[15]
[15, 16]
HIGH to Write End
2
[15, 16]
[15]
/I
as shown in
"AC Test Loads and Waveforms" on page
OL
OH
is less than t
, t
is less than t
HZCE
LZCE
HZBE
= V
1
4.
application note AN13842
, t
is less than t
, and t
LZBE
HZOE
LZOE
, BHE or BLE or both = V
, and CE
IL
IL
2
®
CY62167E MoBL
45 ns
Unit
Min
Max
45
ns
45
ns
10
ns
45
ns
22
ns
5
ns
18
ns
10
ns
18
ns
0
ns
45
ns
45
ns
10
ns
18
ns
45
ns
35
ns
35
ns
0
ns
0
ns
35
ns
35
ns
25
ns
0
ns
18
ns
10
ns
(typ)/2, input pulse levels
CC
for further clarification.
is less than t
for any device.
HZWE
LZWE
= V
. All signals must be active to initiate
IH
Page 5 of 12
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