Cypress Semiconductor STK11C68-5 Технічна специфікація - Сторінка 8
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SRAM Write Cycle
Parameter
Cypress
Alt
Parameter
t
t
Write Cycle Time
WC
AVAV
t
t
t
Write Pulse Width
PWE
WLWH,
WLEH
t
t
t
Chip Enable To End of Write
SCE
ELWH,
ELEH
t
t
t
Data Setup to End of Write
SD
DVWH,
DVEH
t
t
t
Data Hold After End of Write
HD
WHDX,
EHDX
t
t
t
Address Setup to End of Write
AW
AVWH,
AVEH
t
t
t
Address Setup to Start of Write
SA
AVWL,
AVEL
t
t
t
Address Hold After End of Write
HA
WHAX,
EHAX
[6,7]
t
Write Enable to Output Disable
t
WLQZ
HZWE
[6]
t
Output Active After End of Write
t
WHQX
LZWE
Switching Waveforms
ADDRESS
CE
WE
DATA IN
DATA OUT
ADDRESS
CE
WE
DATA IN
DATA OUT
Notes
7. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
8. CE or WE must be greater than V
Document Number: 001-51001 Rev. *A
Description
Figure 8. SRAM Write Cycle 1: WE Controlled
t
SA
PREVIOUS DATA
Figure 9. SRAM Write Cycle 2: CE and OE Controlled
t
SA
HIGH IMPEDANCE
during address transitions.
IH
STK11C68-5 (SMD5962-92324)
35 ns
Min
Max
35
25
25
12
0
25
0
0
13
5
t
WC
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
t
HZWE
HIGH IMPEDANCE
t
WC
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
45 ns
55 ns
Min
Max
Min
Max
45
55
30
45
30
45
15
30
0
0
30
45
0
0
0
0
15
35
5
5
[7, 8]
t
HA
t
HD
t
LZWE
[7, 8]
t
HA
t
HD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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