Cypress Semiconductor STK12C68-5 Технічна специфікація - Сторінка 12
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Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
Parameter
Alt
[14]
t
t
RC
AVAV
[17]
t
t
SA
AVEL
[17]
t
t
CW
ELEH
[17]
t
t
HACE
ELAX
t
RECALL
Switching Waveform
ADDRESS
t
SA
CE
OE
DQ (DATA)
Notes
17. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
18. The six consecutive addresses must be read in the order listed in
Document Number: 001-51026 Rev. **
[18]
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Figure 13. CE Controlled Software STORE/RECALL Cycle
t
RC
A
D
D
R
E
S
S
#
1
t
SCE
t
HACE
DATA VALID
Table 1
STK12C68-5 (SMD5962-94599)
Min
35
0
25
20
t
RC
A
D
D
R
E
S
S
#
6
DATA VALID
on page 6. WE must be HIGH during all six consecutive cycles.
35 ns
55 ns
Max
Min
Max
55
0
30
20
20
20
[18]
t
/ t
STORE
RECALL
HIGH IMPEDANCE
Page 12 of 18
Unit
ns
ns
ns
ns
μs
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