Cypress Semiconductor STK15C88 Технічна специфікація - Сторінка 8

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AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Alt
Parameter
t
t
ACE
ELQV
[5]
t
t
t
RC
AVAV,
ELEH
[6]
t
t
AA
AVQV
t
t
DOE
GLQV
[6]
t
t
OHA
AXQX
[7]
t
t
LZCE
ELQX
[7]
t
t
HZCE
EHQZ
[7]
t
t
LZOE
GLQX
[7]
t
t
HZOE
GHQZ
[4]
t
t
PU
ELICCH
[4]
t
t
PD
EHICCL

Switching Waveforms

Notes
5. WE must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles.
6. I/O state assumes CE and OE < V
7. Measured ±200 mV from steady state output voltage.
Document Number: 001-50593 Rev. **
Description
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Figure 5. SRAM Read Cycle 1: Address Controlled
Figure 6. SRAM Read Cycle 2: CE and OE Controlled
and WE > V
; device is continuously selected.
IL
IH
STK15C88
25 ns
45 ns
Min
Max
Min
Max
25
25
45
25
10
5
5
5
5
10
0
0
10
0
0
25
[5, 7]
[5]
Unit
45
ns
ns
45
ns
20
ns
ns
ns
15
ns
ns
15
ns
ns
45
ns
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