DG NVMe-IP Instrucción - Página 5
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5) Set SW3[1] /[2]/ [6]/ [8] = OFF position to enable JTAG of HPS, FPGA, and MAX, as
shown in Figure 2-4.
6) Connect FPGA power adapter to FPGA board, as shown in Figure 2-5.
7) Power on FPGA development board.
8) Open
Serial
BaudRate=115,200, Data=8 bit, Non-Parity, and Stop=1.
9) On PC Serial console, please wait Linux boot-up until login required, as shown in Figure
2-6.
19-Feb-18
Figure 2-4 JTAG Enable for Arria10 SoC board
Figure 2-5 Power on FPGA board
console
software
Figure 2-6 Linux Boot-up
such
as
HyperTerminal.
Software
setting
Page 5
is