Dell 3250 Manual del producto - Página 22
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BIOS POST Error Codes and Messages
Error
Error Message and Character
Code
Attributes
8197
Processor speeds mismatched
DFLT/RED_BLACK
8210
Processor 1 Late Self Test
Failed: Performance restricted
DFLT/RED_BLACK
8211
Processor 2 Late Self Test
Failed: Performance restricted
DFLT/RED_BLACK
8220
Processor 1 Late Self Test
Failed: Functionally restricted
DFLT/RED_BLACK
8221
Processor 2 Late Self Test
Failed: Functionally restricted
DFLT/RED_BLACK
8230
Processor 1 Late Self Test
Failed: Catastrophic failure
DFLT/RED_BLACK
8231
Processor 2 Late Self Test
Failed: Catastrophic failure
DFLT/RED_BLACK
8300
Baseboard Management
Controller failed to function
DFLT/RED_BLACK
8306
OS boot watchdog timer failure
DFLT/RED_BLACK
84F3
Baseboard Management
Controller in Update Mode
DFLT/RED_BLACK
84FF
System Event Log Full
DFLT/RED_BLACK
8500
Multi-bit Error Detected Row1.
Row mapped out
WARN/YELLOW_BLACK
8501
Multi-bit Error Detected Row2.
Row mapped out
WARN/YELLOW_BLACK
8504
Persistent Single-bit Error
Detected Row1. Row mapped
out. WARN/YELLOW_BLACK
8505
Persistent Single-bit Error
Detected Row2. Row mapped
out. WARN/YELLOW_BLACK
16
Pause on
Boot
No
BIOS compared Processors and determined
mismatched speeds, both processors will be
Performance restricted, both will default to run at lower
of the two speeds. If both processors are identical -
Refer to "Processor" in Debug Methodology and failure
Isolation section.
Yes
Failure identified in late self-test, Processor 1 will be
Performance restricted. Refer to "Processor Late Self
test" in Debug Methodology and failure Isolation
section.
Yes
Failure identified in late self-test, Processor 2 will be
Performance restricted. Refer to "Processor Late Self
test" in Debug Methodology and failure Isolation
section.
Yes
Failure identified in late self-test, Processor 1 will be
Functionally restricted. Refer to "Processor Late Self
test" in Debug Methodology and failure Isolation
section.
Yes
Failure identified in late self-test, Processor 2 will be
Functionally restricted. Refer to "Processor Late Self
test" in Debug Methodology and failure Isolation
section.
Yes
Failure identified in late self-test, Processor 1 will be
disabled. Refer to "Processor Late Self test" in Debug
Methodology and failure Isolation section.
Yes
Failure identified in late self-test, Processor 2 will be
disabled. Refer to "Processor Late Self test" in Debug
Methodology and failure Isolation section.
Yes
Check to see that the jumper at J5H4 is in position 1-2
=normal, (position 2-3 is update mode).
If Issue persists replace main board.
Yes
System exceeded 6-minute watchdog timer on boot
cycle. Refer to "Watch dog timer" for detail.
Yes
Check to see that the jumper at J5H4 is in position 1-2
=normal, (position 2-3 is update mode).
If Issue persists replace main board.
Yes
The System Event Log is Full, Save or Clear SEL, See
section on "Thresholding"
Yes
The multi-bit error is detected on a DIMM(s) in Row 1;
Row disabled, Refer to "Memory" in Debug
Methodology and failure Isolation section.
Yes
The multi-bit error is detected on a DIMM(s) in Row 2;
Row disabled, Refer to "Memory" in Debug
Methodology and failure Isolation section.
Yes
Issue with DIMM address or data line likely affecting
multiple DIMMs (otherwise ECC should recover) in
Row 1; Row disabled, Refer to "Memory" in Debug
Methodology and failure Isolation section.
Yes
Issue with DIMM address or data line likely affecting
multiple DIMMs (otherwise ECC should recover) in
Row 2; Row disabled, Refer to "Memory" in Debug
Methodology and failure Isolation section.
Intel® Server Platform SR870BH2
Failure
Revision 1.1