Digilent NetFPGA-SUME Manual de referencia - Página 7
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NetFPGA-SUME™ Reference Manual
Additionally, the LTC2974 can margin and trim up to four output voltages using a 10-bit DAC, allowing for more
precise output voltages.
Figure 7 depicts the connections between the two LTC2974s, as well as the signals that are used to control the
power on and off sequence. When the input voltage (VCC12V0) exceeds 10 volts, the LTC2974s will perform a
power on sequence when the power switch (SW1) is placed in the "ON" position. When a power on sequence is
performed, the rails come up in the following order:
1. VCC1V0
2. VCC1V8
3. VCC2V0
4. MGTAVCC
5. MGTAVTT
6. VCC3V3
7. VCC1V5, QDRVTT, and DDRVTT
8. MGTVAUX
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Figure 7. LTC2974 sequencer and supervisor.
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