Cypress Semiconductor STK12C68-5 Hoja de especificaciones - Página 10
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SRAM Write Cycle
Parameter
Cypress
Alt
Parameter
t
t
WC
AVAV
t
t
t
PWE
WLWH,
WLEH
t
t
t
SCE
ELWH,
ELEH
t
t
t
SD
DVWH,
DVEH
t
t
t
HD
WHDX,
EHDX
t
t
t
AW
AVWH,
AVEH
t
t
t
SA
AVWL,
AVEL
t
t
t
HA
WHAX,
EHAX
[9,10]
t
t
HZWE
WLQZ
[9]
t
t
LZWE
WHQX
Switching Waveforms
ADDRESS
CE
WE
DATA IN
DATA OUT
ADDRESS
CE
WE
DATA IN
DATA OUT
Notes
10. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
11. HSB must be high during SRAM Write cycles.
12. CE or WE must be greater than V
Document Number: 001-51026 Rev. **
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
Figure 10. SRAM Write Cycle 1: WE Controlled
t
AW
t
SA
t
HZWE
PREVIOUS DATA
Figure 11. SRAM Write Cycle 2: CE Controlled
t
SA
HIGH IMPEDANCE
during address transitions.
IH
STK12C68-5 (SMD5962-94599)
35 ns
Min
Max
35
25
25
12
0
25
0
0
13
5
t
WC
t
HA
t
SCE
t
PWE
t
t
SD
HD
DATA VALID
HIGH IMPEDANCE
t
WC
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
55 ns
Min
Max
55
45
45
25
0
45
0
0
15
5
[11, 12]
t
LZWE
[11, 12]
t
HA
t
HD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 10 of 18
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