Cypress Semiconductor STK12C68-5 Hoja de especificaciones - Página 11
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AutoStore or Power Up RECALL
Parameter
Alt
[13]
t
t
RESTORE
HRECALL
[14, 15, 16]
t
t
HLHZ
STORE
[9, 15]
t
t
t
HLQZ ,
BLQZ
DELAY
V
SWITCH
V
RESET
t
VCCRISE
[11]
t
VSBL
Switching Waveform
WE
Notes
13. t
starts from the time V
HRECALL
CC
14. CE and OE low for output behavior.
15. CE and OE low and WE high for output behavior.
16. HSB is asserted low for 1us when V
takes place.
Document Number: 001-51026 Rev. **
Description
Power up RECALL Duration
STORE Cycle Duration
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
Low Voltage Reset Level
V
Rise Time
CC
Low Voltage Trigger (V
SWITCH
Figure 12. AutoStore/Power Up RECALL
rises above V
.
SWITCH
drops through V
. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store
CAP
SWITCH
STK12C68-5 (SMD5962-94599)
STK12C68-5
Min
1
4.0
150
) to HSB Low
Unit
Max
μs
550
10
ms
μs
4.5
V
3.9
V
μs
300
ns
Page 11 of 18
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