Cypress Semiconductor STK14C88-3 Hoja de especificaciones - Página 9

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AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Alt
Parameter
t
t
ACE
ELQV
[9]
t
t
t
RC
AVAV,
ELEH
[10]
t
t
AA
AVQV
t
t
DOE
GLQV
[10]
t
t
OHA
AXQX
[11]
t
t
LZCE
ELQX
[11]
t
t
HZCE
EHQZ
[11]
t
t
LZOE
GLQX
[11]
t
t
HZOE
GHQZ
[8]
t
t
PU
ELICCH
[8]
t
t
PD
EHICCL

Switching Waveforms

Notes
9. WE and HSB must be HIGH during SRAM Read Cycles.
10. I/O state assumes CE and OE < V
11. Measured ±200 mV from steady state output voltage.
Document Number: 001-50592 Rev. **
Description
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Figure 7. SRAM Read Cycle 1: Address Controlled
Figure 8. SRAM Read Cycle 2: CE and OE Controlled
and WE > V
; device is continuously selected.
IL
IH
STK14C88-3
35 ns
45 ns
Min
Max
Min
Max
35
35
45
35
15
5
5
5
5
13
0
0
13
0
0
35
[9, 10]
[9]
Unit
45
ns
ns
45
ns
20
ns
ns
ns
15
ns
ns
15
ns
ns
45
ns
Page 9 of 17
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