DG FPGA Mise en place - Page 10

Parcourez en ligne ou téléchargez le pdf Mise en place pour {nom_de_la_catégorie} DG FPGA. DG FPGA 14 pages.
Également pour DG FPGA : Mise en place (5 pages), Mise en place (20 pages), Mise en place (8 pages), Mise en place (10 pages), Mise en place (18 pages)

Imprimer la page
DG FPGA Mise en place
dg_nvmeip_raid0x2_fpgasetup_xilinx_en.doc
6) For KCU105 board by AB17, open Serial console to connect with Enhanced COM port
(Buad rate=115,200 Data=8 bit Non-Parity Stop=1). The console shows System
Controller menu, as shown in Figure 2-7. To set VADJ of FMC to 1.8V, the following step is
recommended.
i. Input '4' to select Adjust FMC Settings.
ii. Input '4' to set FMC VADJ to 1.8V.
iii. Input '0' to return to Main Menu.
iv. Input '2' to get PMBUS Voltages.
v. Input '7' to get VADJ1V8 Voltage. The output voltage of this menu must be equal to
1.8V to confirm that VADJ has been set completely.
For more details of System Controller, please check "UG917 KCU105 Board User Guide"
in section "Appendix C: System Controller".
https://www.xilinx.com/support/documentation/boards_and_kits/kcu105/ug917-kcu105-e
val-bd.pdf
15-Jul-21
Figure 2-7 Setting VADJ on FMC for KCU105
Page 10