Chrontel CH7034B Notes d'application

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AN-B013

Application Notes

Chrontel

PCB Layout and Design Guide for CH7034B HDTV/VGA/LVDS Encoder

1.0 I

NTRODUCTION

Chrontel CH7034B is specifically designed for a portable system that requires connections to LCD display, High

Definition Television (HDTV) or RGB (VGA) monitor. With its advanced video encoder, flexible scaling engine and

easy-to- configure audio interface, the CH7034B satisfies manufactures' product display requirements and reduces their

cost of development and time-to-market.

This application note focuses only on the basic PCB layout and design guidelines for CH7034B HDTV/VGA/LVDS

encoder. Guidelines in component placement, power supply decoupling, grounding, input /output signal interface are

discussed in this document.

The discussion and figures that follow reflect and describe connections based on the 88-pin QFN package of the

CH7034B. Please refer to the CH7034B datasheet for the details of the pin assignments.

2.0 C

OMPONENT

LACEMENT AND

ESIGN

ONSIDERATIONS

Components associated with the CH7034B should be placed as close as possible to the respective pins. The following

discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the placement

and layout of components associated with these pins.

2.1

Power Supply Decoupling

The optimum power supply decoupling is accomplished by placing a 0.1μF ceramic capacitor to each of the power

supply pins as shown in Figure 1. These capacitors (C1, C2, C4, C5, C7, C8, C10, C11, C13, C14, C16, C18, C19, C22)

should be connected as close as possible to their respective power and ground pins using short and wide traces to

minimize lead inductance. Whenever possible, a physical connecting trace should connect the ground pins of the

decoupling capacitors to the CH7034B ground pins, in addition to ground vias.

2.1.1

Ground Pins

The analog and digital grounds of the CH7034B should be connected to a common ground plane to provide a low

impedance return path for the supply currents. Whenever possible, each of the CH7034B ground pins should be

connected to its respective decoupling capacitor ground lead directly, then connected to the ground plane through a

ground via. Short and wide traces should be used to minimize the lead inductance. Refer to Table 1 for the Ground pins

assignment.

2.1.2 Power Supply Pins

The power supply include AVDD, AVDD_DAC, VDDH, AVDD_PLL, VDDIO, DVDD, VDDMQ, VDDMS.

Refer toTable1 for the Power supply pins assignment. Refer to Figure 1 for Power Supply Decoupling.

206-1000-013

Rev1.4,

06/30/2020