Chrontel CH7034B Notes d'application - Page 10
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2.8
LVDS Output
The LVDS output signals are LDCx* and LDCx. The LVDS is a differential interface with a nominal swing 200mV.
The following rules applies to the signals:
1. Keep traces as short as possible.
2. Make these traces have 100 ohm differential impedance.
3. Trace widths should be 5 mils.
4. Intra Pair spacing (spacing between the "+" and "-" pairs) should be 7mils.
5. Inter Pair spacing (spacing between one differential pair and another) should be a minimum of 20 mils.
6. Difference in trace lengths between "+" and "-" pairs should be within 5mils.
7. Difference in trace lengths among Inter pairs should be within 10mils.
8. "+" and "-" pairs should be routed in parallel.
2.9
Important Design Considerations
• LVDS Power
Close attention must be paid to the power supplied to the LVDS backlight and the LVDS panel. Power requirements
may differ from panel to panel. Please check the panels' power and backlight voltage specifications.
ENABLK(pin58) and ENAVDD(pin57) of the CH7034B can be used as control signal to turn on the power to the
LVDS backlight and the LVDS logic circuitry.
• PWM
PWM can be used to control the backlight luminance level. The duty cycle of pwm wave can varies between 0 and 1
with a step of 1/255 and the frequency of PWM wave can be 100Hz, 200Hz, 2KHz, 4KHz, 16KHz, 32KHz, 64KHz,
and 128KHz via register setting.
2.10 Thermal Exposed Pad Package
The CH7034B is available in 88-pin QFN package with thermal exposed pad package. The advantage of the thermal
exposed pad package is that the heat can be dissipated through the ground layer of the PCB more efficiently. When
properly implemented, the exposed pad package provides a means of reducing the thermal resistance of the
CH7034B.
Careful attention to the design of the PCB layout is required for good thermal performance. For maximum heat
dissipation, the exposed pad of the package should be soldered to the PCB as shown in Figure 10.
Die
Exposed Pad
Solder
PCB
Thermal pad dimension is from 6.6mm to 6.9mm (min to max), 6.6mm x 6.6mm is the minimum size recommended
for the thermal pad, and 6.9mm x 6.9mm is the maximum size. The thermal land pattern should have a 5x5 grid
array of 1.0 mm pitch thermal vias connected to the ground layer of the PCB. These vias should be 0.3mm in
diameter with 1 oz copper via barrel plating. Please refer to Figure 11.
10
Figure 10: Cross-section of exposed pad package
206-1000-013
Rev1.4,
AN-B013
Pin
06/30/2020