Cypress Semiconductor CY7C1231H Fiche technique

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7C1231H. Cypress Semiconductor CY7C1231H 13 pages. Cypress 2-mbit (128k x 18) flow-through sram with nobl architecture specification sheet

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Features
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 128K x 18 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
— 6.5 ns (133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed write
• Asynchronous Output Enable
• Offered in JEDEC-standard lead-free 100-pin TQFP
package
• Burst Capability—linear or interleaved burst order
• Low standby power
Logic Block Diagram
A0, A1, A
MODE
CE
CLK
C
CEN
ADV/LD
BW
A
BW
B
WE
OE
CE
1
CE
2
CE
3
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-00207 Rev. *B
2-Mbit (128K x 18) Flow-Through SRAM
ADDRESS
A1
REGISTER
D1
A0
D0
BURST
ADV/LD
LOGIC
C
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
•
198 Champion Court
with NoBL™ Architecture
Functional Description
The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1231H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
) and a Write Enable (WE) input. All writes are
[A:B]
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
A1'
Q1
A0'
Q0
MEMORY
WRITE
ARRAY
DRIVERS
INPUT
REGISTER
,
•
San Jose
CA 95134-1709
CY7C1231H
[1]
, CE
, CE
) and an
1
2
3
O
U
T
P
D
S
U
A
E
T
T
N
A
S
B
E
U
S
DQs
F
T
DQP
A
A
F
E
DQP
B
M
E
E
P
R
R
S
S
I
N
E
G
E
•
408-943-2600
Revised April 26, 2006
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