Cypress Semiconductor CY7C1231H Fiche technique - Page 4

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7C1231H. Cypress Semiconductor CY7C1231H 13 pages. Cypress 2-mbit (128k x 18) flow-through sram with nobl architecture specification sheet

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Functional Overview

The CY7C1231H is a synchronous flow-through burst SRAM

designed specifically to eliminate wait states during

Write-Read transitions. All synchronous inputs pass through

input registers controlled by the rising edge of the clock. The

clock signal is qualified with the Clock Enable input signal

(CEN). If CEN is HIGH, the clock signal is not recognized and

all internal states are maintained. All synchronous operations

are qualified with CEN. Maximum access delay from the clock

rise (t

) is 6.5 ns (133-MHz device).

CDV

Accesses can be initiated by asserting all three Chip Enables

(CE

, CE

) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, depending on

the status of the Write Enable (WE). BW

conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

and CE

are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and 4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory array

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the output buffers. The data is available within 6.5

ns (133-MHz device) provided OE is active LOW. After the first

clock of the read access, the output buffers are controlled by

OE and the internal control logic. OE must be driven LOW in

order for the device to drive out the requested data. On the

subsequent clock, another operation (Read/Write/Deselect)

can be initiated. When the SRAM is deselected at clock rise

by one of the chip enable signals, its output will be tri-stated

immediately.

Burst Read Accesses

The CY7C1231H has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address into the

SRAM, as described in the Single Read Access section above.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst

mode, a HIGH selects an interleaved burst sequence. Both

burst counters use A0 and A1 in the burst sequence, and will

wrap around when incremented sufficiently. A HIGH input on

ADV/LD will increment the internal burst counter regardless of

the state of Chip Enable inputs or WE. WE is latched at the

beginning of a burst cycle. Therefore, the type of access (Read

or Write) is maintained throughout the burst sequence.

Document #: 001-00207 Rev. *B

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

and CE

is asserted LOW. The address presented to the address bus

is loaded into the Address Register. The write signals are

latched into the Control Logic block. The data lines are

automatically tri-stated regardless of the state of the OE input

signal. This allows the external logic to present the data on

DQs and DQP

On the next clock rise the data presented to DQs and DQP

(or a subset for Byte Write operations, see Truth Table for

details) inputs is latched into the device and the write is

complete. Additional accesses (Read/Write/Deselect) can be

initiated on this cycle.

The data written during the Write operation is controlled by

can be used to

[A:B]

capability that is described in the Truth Table. Asserting the

Write Enable input (WE) with the selected Byte Write Select

input will selectively write to only the desired bytes. Bytes not

selected during a Byte Write operation will remain unaltered.

, CE

) and an

A synchronous self-timed write mechanism has been provided

to simplify the Write operations. Byte Write capability has been

included in order to greatly simplify Read/Modify/Write

sequences, which can be reduced to simple byte write opera-

tions.

Because the CY7C1231H is a common I/O device, data

should not be driven into the device while the outputs are

active. The Output Enable (OE) can be deasserted HIGH

before presenting data to the DQs and DQP

, CE

so will tri-state the output drivers. As a safety precaution, DQs

and DQP

portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1231H has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Write operations without reasserting the address inputs.

ADV/LD must be driven LOW in order to load the initial

address, as described in the Single Write Access section

above. When ADV/LD is driven HIGH on the subsequent clock

rise, the Chip Enables (CE

ignored and the burst counter is incremented. The correct

in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation "sleep" mode. Two

clock cycles are required to enter into or exit from this "sleep"

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the "sleep" mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the "sleep" mode. CE

the duration of t

are ALL asserted active, and (3) the Write signal WE

[A:B]

signals. The CY7C1231H provides Byte Write

[A:B]

.are automatically tri-stated during the data

[A:B]

, CE

, and CE

inputs must be driven in each cycle of the burst write,

[A:B]

, CE

, and CE

after the ZZ input returns LOW.

ZZREC

CY7C1231H

, CE

[A:B]

inputs. Doing

[A:B]

) and WE inputs are

, must remain inactive for

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