Cypress Semiconductor CY7C1333H Fiche technique - Page 5

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7C1333H. Cypress Semiconductor CY7C1333H 13 pages. Cypress 2-mbit (64k x 32) flow-through sram with nobl architecture specification sheet

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Linear Burst Address Table (MODE = GND)
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
10
10
11
11
00
ZZ Mode Electrical Characteristics
Parameter
I
Sleep mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
t
ZZ Active to sleep current
ZZI
t
ZZ inactive to exit sleep current
RZZI
[2, 3, 4, 5, 6, 7, 8]
Truth Table
ADDRESS
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect
Cycle
READ Cycle
External
(Begin Burst)
READ Cycle
(Continue Burst)
NOP/DUMMY READ
External
(Begin Burst)
DUMMY READ
(Continue Burst)
WRITE Cycle
External
(Begin Burst)
WRITE Cycle
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE CLOCK
Current
EDGE (Stall)
Sleep MODE
Notes:
2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BW
, and WE. See Truth Table for Read/Write.
[A:D]
4. When a Write cycle is detected, all I/Os are three-stated, even during Byte Writes.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQ
or when the device is deselected, and DQ
Document #: 001-00209 Rev. **
PRELIMINARY
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
00
00
01
01
10
Description
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Used
CE
CE2
CE
1
3
None
H
X
X
None
X
X
H
None
X
L
X
None
X
X
X
L
H
L
Next
X
X
X
L
H
L
Next
X
X
X
L
H
L
Next
X
X
X
None
L
H
L
Next
X
X
X
X
X
X
None
X
X
X
= data when OE is active.
s
Interleaved Burst Sequence
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
00
10
11
11
10
Test Conditions
− 0.2V
DD
− 0.2V
DD
ZZ
ADV/LD
WE
BW
X
L
L
X
X
L
L
X
X
L
L
X
X
L
H
X
X
L
L
H
X
L
H
X
X
L
L
H
X
L
H
X
X
L
L
L
L
L
H
X
L
L
L
L
H
L
H
X
H
L
X
X
X
H
X
X
X
CY7C1333H
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
10
00
01
01
00
Min.
Max.
Unit
40
mA
2t
ns
CYC
2t
ns
CYC
2t
ns
CYC
0
ns
OE CEN
CLK
DQ
X
L
L->H
Three-State
X
L
L->H
Three-State
X
L
L->H
Three-State
X
L
L->H
Three-State
L
L
L->H
Data Out (Q)
L
L
L->H
Data Out (Q)
H
L
L->H
Three-State
H
L
L->H
Three-State
X
L
L->H
Data In (D)
X
L
L->H
Data In (D)
X
L
L->H
Three-State
X
L
L->H
Three-State
X
H
L->H
-
X
X
X
Three-State
= Three-state when OE is inactive
s
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