Cypress Semiconductor CY7C1350G Fiche technique - Page 10

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7C1350G. Cypress Semiconductor CY7C1350G 16 pages. Cypress 4-mbit (128k x 36) pipelined sram with nobl architecture specification sheet

Imprimer la page

Switching Waveforms

[19, 20, 21]
Read/Write Timing
1
CLK
t
t
CENS
CENH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
[A:D]
A1
ADDRESS
t
t
AS
AH
Data
In-Out (DQ)
OE
WRITE
D(A1)
Notes:
19. For this waveform ZZ is tied LOW.
20. When CE is LOW, CE
is LOW, CE
1
21. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05524 Rev. *F
2
3
4
t CYC
t
t
CH
CL
A2
A3
t
t
DS
DH
D(A1)
D(A2)
WRITE
BURST
READ
D(A2)
WRITE
Q(A3)
D(A2+1)
DON'T CARE
is HIGH and CE
is LOW. When CE is HIGH, CE
2
3
5
6
7
A4
A5
t
CO
t
t
DOH
CLZ
D(A2+1)
Q(A3)
Q(A4)
t
OEHZ
READ
BURST
WRITE
Q(A4)
READ
D(A5)
Q(A4+1)
UNDEFINED
is HIGH or CE
is LOW or CE
1
2
CY7C1350G
8
9
10
A6
A7
t
t
OEV
CHZ
Q(A4+1)
D(A5)
Q(A6)
t
DOH
t
OELZ
READ
WRITE
DESELECT
Q(A6)
D(A7)
is HIGH.
3
Page 10 of 15
[+] Feedback