Cypress Semiconductor CY7C1350G Fiche technique - Page 9

Parcourez en ligne ou téléchargez le pdf Fiche technique pour {nom_de_la_catégorie} Cypress Semiconductor CY7C1350G. Cypress Semiconductor CY7C1350G 16 pages. Cypress 4-mbit (128k x 36) pipelined sram with nobl architecture specification sheet

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Switching Characteristics

Parameter
Description
t
V
(typical) to the first Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid After CLK Rise
CO
t
Data Output Hold After CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
t
OE LOW to Output Valid
OEV
t
OE LOW to Output Low-Z
OELZ
t
OE HIGH to Output High-Z
OEHZ
16]
Set-up Times
t
Address Set-up Before CLK Rise
AS
t
ADV/LD Set-up Before CLK Rise
ALS
t
GW, BW
Set-Up Before CLK Rise
WES
X
t
CEN Set-up Before CLK Rise
CENS
t
Data Input Set-up Before CLK Rise
DS
t
Chip Enable Set-Up Before CLK
CES
Rise
Hold Times
t
Address Hold After CLK Rise
AH
t
ADV/LD Hold after CLK Rise
ALH
t
GW, BW
Hold After CLK Rise
WEH
X
t
CEN Hold After CLK Rise
CENH
t
Data Input Hold After CLK Rise
DH
t
Chip Enable Hold After CLK Rise
CEH
Notes:
13. This part has a voltage regulator internally; t
can be initiated.
14. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
15. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
17. Timing reference level is 1.5V when V
18. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05524 Rev. *F
Over the Operating Range
–250
Min. Max. Min. Max.
[13]
1
4.0
1.7
1.7
1.0
[14, 15, 16]
0
[14, 15, 16]
[14, 15, 16]
0
[14, 15,
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
is the time that the power needs to be supplied above V
POWER
is less than t
and t
OEHZ
OELZ
CHZ
= 3.3V and is 1.25V when V
DDQ
DDQ
[17, 18]
–200
–166
Min.
Max. Min. Max. Min. Max. Unit
1
1
5.0
6.0
2.0
2.5
2.0
2.5
2.6
2.8
3.5
1.0
1.5
0
0
2.6
2.8
3.5
2.6
2.8
3.5
0
0
2.6
2.8
3.5
1.2
1.5
1.2
1.5
1.2
1.5
1.2
1.5
1.2
1.5
1.2
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
minimum initially before a Read or Write operation
DD
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
= 2.5V.
CY7C1350G
–133
–100
1
1
ms
7.5
10
ns
3.0
3.5
ns
3.0
3.5
ns
4.0
4.5
ns
1.5
1.5
ns
0
0
ns
4.0
4.5
ns
4.0
4.5
ns
0
0
ns
4.0
4.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
Page 9 of 15
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