Cypress CY62157EV18 Scheda tecnica

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Features
• Very high speed: 55 ns
• Wide voltage range: 1.65V–2.25V
• Pin Compatible with CY62157DV18 and CY62157DV20
• Ultra low standby power
— Typical Standby current: 2 µA
— Maximum Standby current: 8 µA
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package
Functional Description
The CY62157EV18 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
Product Portfolio
Product
Min
CY62157EV18
1.65
Notes
1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" located at
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
Cypress Semiconductor Corporation
Document #: 38-05490 Rev. *D
, CE
and OE features
1
2
[1]
®
) in
Speed
V
Range (V)
CC
(ns)
[2]
Max
Typ
1.8
2.25
55
•
198 Champion Court
CY62157EV18 MoBL
8-Mbit (512K x 16) Static RAM
deselected (CE
HIGH or CE
1
2
HIGH). The input and output pins (IO
placed in a high impedance state when:
• Deselected (CE
HIGH or CE
1
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or
• Write operation is active (CE
LOW).
Write to the device by taking Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO
written into the location specified on the address pins (A
through A
). If Byte High Enable (BHE) is LOW, then data
18
from IO pins (IO
through IO
8
specified on the address pins (A
Read from the device by taking Chip Enables (CE
CE
HIGH) and Output Enable (OE) LOW while forcing the
2
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appear on IO
to IO
. If Byte High Enable (BHE) is LOW,
0
7
then data from memory appears on IO
Table" on page 9
for a complete description of read and write
modes.
Power Dissipation
Operating I
, (mA)
CC
f = f
f = 1MHz
[2]
[2]
Max
Typ
Typ
1.8
3
18
http://www.cypress.com.
= V
CC
,
•
San Jose
CA 95134-1709
LOW or both BHE and BLE are
through IO
) are
0
15
LOW)
2
LOW, CE
HIGH and WE
1
2
LOW and CE
1
through IO
), is
0
7
) is written into the location
15
through A
).
0
18
LOW and
1
to IO
. See the
"Truth
8
15
Standby, I
(µA)
SB2
max
[2]
Max
Max
Typ
25
2
8
, T
= 25°C.
CC(typ)
A
•
408-943-2600
Revised March 30, 2007
®
2
0
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