Cypress Semiconductor CY7C1344H Scheda tecnica - Pagina 11

Sfoglia online o scarica il pdf Scheda tecnica per Hardware del computer Cypress Semiconductor CY7C1344H. Cypress Semiconductor CY7C1344H 15. Cypress 2-mbit (64k x 36) flow-through sync sram specification sheet

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Timing Diagrams
(continued)
[16, 17]
Write Cycle Timing
CLK
t
CH
t ADS
t ADH
ADSP
ADSC
t AS
t AH
ADDRESS
A1
Byte write signals are ignored for first cycle when
ADSP initiates burst.
BWE,
BW
[A:D]
GW
t CES
t CEH
CE
ADV
OE
Data in (D)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Note:
17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Document #: 001-00211 Rev. *B
t CYC
t
CL
t ADS
t ADH
A2
t
t
DS
DH
D(A2)
D(A1)
Single WRITE
DON'T CARE
ADSC extends burst.
t
t
WES
WEH
ADV suspends burst.
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
BURST WRITE
UNDEFINED
LOW.
[A:D]
CY7C1344H
t ADS
t ADH
A3
t WES
t WEH
t ADVS
t ADVH
D(A3)
D(A3 + 1)
D(A3 + 2)
Extended BURST WRITE
Page 11 of 15
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