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P C B L a y o u t a n d D e s i g n G u i d e f o r C H 7 5 1 5 A
I
1.0
NTRODUCTION
Chrontel's CH7515A is a low-cost, low-power semiconductor device that translates the eDP/DP signal to the LVDS
in form of RGB. This innovative eDP/DP receiver with integrated 4 channel LVDS transmitters is specially designed
to target the All-In-One and the notebook market segment.
This application note focuses only on the basic PCB layout and design guidelines for CH7515A Embedded Display
Port/ Display Port Receiver with LVDS Transmitter. Guidelines in component placement, power supply decoupling,
grounding, input /output signal interface are discussed in this document.
The discussion and figures that follow reflect and describe connections based on the 128-pin TQFP (14x14mm)
package of the CH7515A. Please refer to the CH7515A datasheet for the details of the pin assignments.
2.0 C
OMPONENT
Components associated with the CH7515A should be placed as close as possible to the respective pins. The following
discussion will describe guidelines on how to connect critical pins, as well as describe the guidelines for the
placement and layout of components associated with these pins.
2.1
Power Supply Decoupling
The optimum power supply decoupling is accomplished by placing a 0.1μF ceramic capacitor to each of the power
supply pins as shown in Figure 1. These capacitors (C2, C3, C4, C5, C8, C9, C10, C11, C14, C15, C16, C17, C19)
should be connected as close as possible to their respective power and ground pins using short and wide traces to
minimize lead inductance. Whenever possible, a physical connecting trace should connect the ground pins of the
decoupling capacitors to the CH7515A and CH716A ground pins, in addition to ground vias.
2.1.1 Ground Pins
The CH7515A should be connected to a common ground plane to provide a low impedance return path for the supply
currents. Whenever possible, each of the CH7515A ground pins should be connected to its respective decoupling
capacitor ground lead directly, and then connected to the ground plane through a ground via. Short and wide traces
should be used to minimize the lead inductance. Refer to Table 1 for the Ground pins assignment.
2.1.2 Power Supply Pins
The power supplies include VDDPLL, DVDD, AVDD, AVCC, VDDRX, and VDDBG. Refer to Table 1 for the
Power supply pins assignment. Refer to Figure 1 for Power Supply Decoupling.
206-1000-021
Rev 1.0
P
LACEMENT AND
2020-07-15
D
C
ESIGN
ONSIDERATIONS
AN-B021
Application Notes
1