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半導体 Chrontel CH7515AのPDF レイアウト設計マニュアルをオンラインで閲覧またはダウンロードできます。Chrontel CH7515A 15 ページ。
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• AUXP and AUXN
These two pins are Display Port AUX channel control that accepts a half-duplex, bi-directional AC-coupled
differential signal.
They must have the AC-coupling capacitors, and 100nF capacitors are recommended in this document, as shown in
Figure 6.
• HPDET
This output pin indicates whether this device is active or not. It also generates interrupt pulse as defined by Display
Port standard. Output voltage is 3.3V. A resistor more than 100K-Ohm should be connected between this pin and
GND, as shown in Figure 6.
2.6
LVDS Signal Pins
• LVDS Outputs (LDxP and LDxN, LCxP and LCxN?)
The LVDS output signals are LDxP and LDxN. The LVDS is a differential interface with a nominal swing 200mV.
The following rules should be applied to the signals:
1. Keep traces as short as possible.
2. Make these traces have 100-ohm differential impedance.
3. Trace widths should be 5 mils.
4. Intra Pair spacing (spacing between the "+" and "-" pairs) should be 7mils.
5. Inter Pair spacing (spacing between one differential pair and another) should be a minimum of 20 mils exclude pin
pitch around.
6. Difference in trace lengths between "+" and "-" pairs should be within 5mils.
7. Difference in trace lengths among Inter pairs should be within 10mils.
8. "+" And "-" pairs should be routed in parallel.
2.7
Audio Output
• IIS
IIS audio output can be configured through programming CH7515A registers. (Refer to Figure 7)
• SPDIF
For SPDIF output, CH7515A support audio sample frequencies from 32Khz to 192kHz. (Refer to Figure 7)
6
U1
95
AU XN
96
AU XP
110
HP DET
R1
100 K
CH 7515A and CH75 16A
Sink
+3. 3V
R3
R4
R5
1M
1M
100 K
U9
95
C3 0.1 uF
AU XN
96
C5 0.1 uF
AU XP
110
HP DET
R7
100 K
CH 7515A and CH75 16A
Sink
Figure 6: CH7515A AUX channel and HPDET
U2
C1 0.1 uF
AU XN
C2 0.1 uF
AU XP
HP DET
R2
GMCH
100 K
Source eDP
+3. 3V
R6
100 K
U1 1
C4 0.1 uF
AU XN
C6 0.1 uF
AU XP
HP DET
R8
100 K
GMCH
Source DP
206-1000-021
AN-B021
Rev 1.0
2020-07-15