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コンピュータ・ハードウェア Cypress Semiconductor CY7B992のPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY7B992 20 ページ。 Cypress programmable skew clock buffer specification sheet
ページを印刷するFigure 1
shows the typical outputs with FB connected to a zero skew output.
FBInput
REFInput
1Fx
3Fx
2Fx
4Fx
(N/A)
LM
LL
LH
LM
(N/A)
LH
ML
ML
(N/A)
MM
MM
MH
(N/A)
HL
MH
HM
(N/A)
HH
HL
(N/A)
HM
(N/A)
LL/HH
DIVIDED
(N/A)
HH
INVERT
Test Mode
The TEST input is a three level input. In normal system
operation, this pin is connected to ground, enabling the
CY7B991 or CY7B992 to operate as explained in
Matrix"
on page
3.
For testing purposes, any of the three level
inputs can have a removable jumper to ground, or be tied LOW
through a 100Ω resistor. This enables an external tester to
change the state of these pins.
Note
4. FB connected to an output selected for "zero" skew (i.e., xF1 = xF0 = MID).
Document Number: 38-07138 Rev. *B
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
– 6t
U
– 4t
U
– 3t
U
– 2t
U
– 1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
"Skew Select
[4]
If the TEST input is forced to its MID or HIGH state, the device
operates with its internal phase locked loop disconnected, and
input levels supplied to REF directly controls all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW), all outputs
function based only on the connection of their own function
selects inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
CY7B991
CY7B992
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