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コンピュータ・ハードウェア Cypress Semiconductor CY7C1338GのPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY7C1338G 18 ページ。 Cypress 4-mbit (128k x 32) flow-through sync sram specification sheet

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Switching Characteristics

Parameter
t
V
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid After CLK Rise
CDV
t
Data Output Hold After CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
t
OE LOW to Output Valid
OEV
t
OE LOW to Output Low-Z
OELZ
t
OE HIGH to Output High-Z
OEHZ
Setup Times
t
Address Set-up Before CLK Rise
AS
t
ADSP, ADSC Set-up Before CLK Rise
ADS
t
ADV Set-up Before CLK Rise
ADVS
t
GW, BWE, BW
WES
t
Data Input Set-up Before CLK Rise
DS
t
Chip Enable Set-up
CES
Hold Times
t
Address Hold After CLK Rise
AH
t
ADSP, ADSC Hold After CLK Rise
ADH
t
GW, BWE, BW
WEH
t
ADV Hold After CLK Rise
ADVH
t
Data Input Hold After CLK Rise
DH
t
Chip Enable Hold After CLK Rise
CEH
Notes:
11. This part has a voltage regulator internally; t
can be initiated.
12. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
13. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing reference level is 1.5V when V
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05521 Rev. *D
Over the Operating Range
Description
(Typical) to the first Access
[12, 13, 14]
[12, 13, 14]
[12, 13, 14]
[12, 13, 14]
Set-up Before CLK Rise
X
Hold After CLK Rise
X
is the time that the power needs to be supplied above V
POWER
is less than t
and t
OEHZ
OELZ
= 3.3V and is 1.25V when V
DDQ
[11, 12, 13, 14, 15, 16]
[11]
is less than t
to eliminate bus contention between SRAMs when sharing the same
CHZ
CLZ
= 2.5V.
DDQ
CY7C1338G
–133
–100
Min.
Max.
Min.
Max.
1
1
7.5
10
2.5
4.0
2.5
4.0
6.5
2.0
2.0
0
0
3.5
3.5
0
0
3.5
1.5
2.0
1.5
2.0
1.5
2.0
1.5
2.0
1.5
1.5
1.5
2.0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
(minimum) initially before a read or write operation
DD
Unit
ms
ns
ns
ns
8.0
ns
ns
ns
3.5
ns
3.5
ns
ns
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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