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コンピュータ・ハードウェア Cypress Semiconductor CY7C1399BのPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor CY7C1399B 11 ページ。 32k x 8 3.3v static ram
ページを印刷するSwitching Characteristics
Parameter
READ CYCLE
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE LOW to Data Valid
ACE
t
OE LOW to Data Valid
DOE
t
OE LOW to Low Z
LZOE
t
OE HIGH to High Z
HZOE
t
CE LOW to Low Z
LZCE
t
CE HIGH to High Z
HZCE
t
CE LOW to Power-Up
PU
t
CE HIGH to Power-Down
PD
[8, 9]
WRITE CYCLE
t
Write Cycle Time
WC
t
CE LOW to Write End
SCE
t
Address Set-Up to Write End
AW
t
Address Hold from Write End
HA
t
Address Set-Up to Write Start
SA
t
WE Pulse Width
PWE
t
Data Set-Up to Write End
SD
t
Data Hold from Write End
HD
t
WE LOW to High Z
HZWE
t
WE HIGH to Low Z
LZWE
Notes:
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and capacitance C
= 30 pF.
OL
OH
L
6.
At any given temperature and voltage condition, t
7.
t
, t
, t
are specified with C
HZOE
HZCE
HZWE
8.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9.
The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
Document #: 38-05071 Rev. *A
[5]
Over the Operating Range
Description
[6]
[6, 7]
[6]
[6, 7]
[8]
[6]
is less than t
, t
HZCE
LZCE
= 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
L
1399B–10
Min.
Max.
10
3
0
3
0
10
8
7
0
0
7
5
0
3
is less than t
, and t
is less than t
HZOE
LZOE
HZWE
and t
.
HZWE
SD
CY7C1399B
1399B–12
Min.
Max.
12
10
12
3
10
12
5
5
0
5
5
3
5
6
0
10
12
12
8
8
0
0
8
7
0
7
7
3
for any given device.
LZWE
Page 4 of 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns