コンピュータ・ハードウェア Cypress Semiconductor Rambus XDR CY24272のPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor Rambus XDR CY24272 13 ページ。 Clock generator with zero sda hold time
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Features
®
■
Meets Rambus
Extended Data Rate (XDR™) clocking
requirements
■
25 ps typical cycle-to-cycle jitter
❐
–135 dBc/Hz typical phase noise at 20 MHz offset
■
100 or 133 MHz differential clock input
■
300–667 MHz high speed clock support
■
Quad (open drain) differential output drivers
■
Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4
■
Spread Aware™
■
2.5V operation
■
28-pin TSSOP package
Logic Block Diagram
REFCLK,REFCLKB
Cypress Semiconductor Corporation
Document Number: 001-42414 Rev. **
®
Rambus
/BYPASS
EN
RegA
RegB
Bypass
MUX
RegC
PLL
RegD
SCL
SDA
ID0
ID1
•
198 Champion Court
XDR™ Clock Generator with
Zero SDA Hold Time
Table 1. Device Comparison
CY24271
SDA hold time = 300 ns
(SMBus compliant)
R
= 200Ω typical
RC
(Rambus standard drive)
EN
EN
EN
EN
,
•
San Jose
CA 95134-1709
CY24272
CY24272
SDA hold time = 0 ns
2
(I
C compliant)
R
= 295Ω minimum
RC
(Reduced output drive)
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
CLK3
CLK3B
•
408-943-2600
Revised November 9, 2007
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