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コンピュータ・ハードウェア Cypress Semiconductor Rambus XDR CY24272のPDF 仕様書をオンラインで閲覧またはダウンロードできます。Cypress Semiconductor Rambus XDR CY24272 13 ページ。 Clock generator with zero sda hold time
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Table 6. Command Code 80h
Bit
Register
7
Reserved
6
MULT2
5
MULT1
4
MULT0
3
RegA
2
RegB
1
RegC
0
RegD
Table 7. Command Code 81h
Bit
Register
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
REFSEL
1
Reserved
0
RegTest
Table 8. Command Code 82h
Bit
Register
7
Device
Revision
6
Number
5
4
3
2
Vendor ID
1
0
Note
5. RW = Read and Write, RO = Read Only, POD = Power on default. See
Document Number: 001-42414 Rev. **
[5]
POD
Type
0
RW
Reserved (no internal function)
0
RW
PLL Multiplier Select (reference
0
RW
1
RW
1
RW
Clock 0 Output Select
1
RW
Clock 1 Output Select
1
RW
Clock 2 Output Select
1
RW
Clock 3 Output Select
[5]
POD
Type
0
RW
Reserved (no internal function)
0
RW
0
RW
0
RW
1
RW
Reserved (must be set to '1' for proper operation)
0
RW
Reference Frequency Select (reference
0
RW
Reserved (must be set to '0' for proper operation)
0
RW
Reserved (must be set to '0' for proper operation)
[5]
POD
Type
?
RO
Contact factory for Device Revision Number information.
?
RO
?
RO
?
RO
?
RO
0
RO
Rambus assigned Vendor ID Code
1
RO
0
RO
Description
Table 3
Description
Description
Table 3
on page 3 for PLL multipliers and
CY24272
on page 3)
Table 3
on page 3)
Table 5
on page 4 for clock output selections.
Page 5 of 13
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