Dantel 49018 설치 및 운영 매뉴얼 - 페이지 3

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CIRCUIT DESCRIPTION

49018-0697 <90-00089>

he functional schematic for the 49018 Station Selector

Subassembly is shown in Fig. 1. The circuit consists of:

♦

6 miniature 10-digit code select switches

♦

Two output station drivers

♦

An address buffer latch

♦

Two address comparators

♦

A digit counter

♦

A clock pulse delay circuit

♦

Two station address latches

♦

An interdigit and reset timer

♦

A supervisory decoder

♦

A busy latch

♦

A busy reset pulse circuit

♦

0 and 1 digit output drivers

In Dantels 440 CMS and TMS single station package, the 49018

subassembly BCD address decoder is controlled by BCD inputs

from the 44020 DTMF Decoder Module. The 49018 provides

buffered outputs for two station addresses. It also includes

buffered outputs for busy control, clear, and 0 and 1 digits.

The outputs are applied to the 44022 Station Interface Module

or the 44023 PABX/Trunk Interface Module of the 440 CMS or

TMS.

Miniature 10-digit switches on the 49018 subassembly are used

to preset the two address codes (station 1 and station 2). These

codes can be one, two, or three digits each. When the correct

incoming BCD address is decoded, the respective station driver

is grounded. At the same time, the 49018 provides a ground

enable output for the ring generator start.

Decoding

The BCD digit inputs from the 44020 DTMF Decoder are loaded

into the address buffer latch using pins P1-1, -2, -3, and -4. The

digits are loaded on the positive edge of the strobe pulse input at

P1-5. The address buffer latch remains in a set state and its

output is applied to both station address comparators.

Refer to Fig. 2 for 49018 Subassembly-to-Host Module pin

connections.

AGE