DAP Technology FireSpy 3200 빠른 시작 매뉴얼 - 페이지 3

{카테고리_이름} DAP Technology FireSpy 3200에 대한 빠른 시작 매뉴얼을 온라인으로 검색하거나 PDF를 다운로드하세요. DAP Technology FireSpy 3200 19 페이지. 1394 analyzer

Chapter 1. Hardware

In order to support the higher speeds this new generation of 1394 bus analyzer has been completely

redesigned. And the 1394 interface is entirely based on DapTechnology's Firewire IP solution FireCore™

which combines both the Physical as well as the Link Layer functionality in one IP block.

Important!

Do not connect or disconnect the FireSpy when the computer is powered on.

Please turn on the connected FireSpy 1600/3200 before starting the computer and do not turn it

off until after the computer is powered down.

General

· S1600 (S3200 for FireSpy3200) capable 1394 PHY is implemented in FPGA allowing more low level

analyzer flexibility

· Supports S800 and S1600 (and S3200 on FireSpy3200) port speeds

· Host connection via PCI Express x4

· Firmware field upgradeable to enable future expansions

· External Trigger Input: 2.5V, (not implemented yet)

· AUX connector for:

· Trigger input and output functions

· Recording external event (not implemented yet)

· Software runs on Windows™ XP and Windows™ 7

· Configurable 1394 Behaviour like:

· Configuration Rom

· Cycle master Capable

· IRM Capable

Monitor

· Displays bus activity:

· Counts packets according to type, speed, ack and error condition

· Counts number of bus resets

Commander

· Reading and/or writing of local and reading of remote PHY registers

· Reading and/or writing of remote memory locations (incl. CSR register space)

· Possibility to graphically view the current Topologies

· Sending of user definable packets (currently only legal packets)

· IIDC Camera Support (under development, requires IIDC Protocol license)

Recorder

· Time stamping of all packets and status events

· Packets hidden by slower connections are visible as 'prefix only' packets

· Extensive packet/event filtering/trigger/search capabilities

· Packet type

· Transmission speed

· Boolean combination of 4 programmable packet sets

· Data payload patterns

· Error conditions

· Various status events

Hardware