4ms PEG 사용자 설명서 - 페이지 2
{카테고리_이름} 4ms PEG에 대한 사용자 설명서을 온라인으로 검색하거나 PDF를 다운로드하세요. 4ms PEG 12 페이지. Pingable envelope generator, eurorack module
페이지 인쇄Features
Basics:
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Dual "pingable" envelope generator – total envelope time is set by a minimum of two pulses
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("ping")
Tap tempo button or external clock/triggers sets the ping time
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Two taps will set the tempo. If a third tap is given close to the tempo to the first two taps, the two
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timing periods will be averaged
Envelope time is a multiple or division of the ping clock (from /8 to x8) set by Ping Div/Mult knob
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and CV
Curve knob and CV control the shape of the output envelope – various combinations of
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exponential, linear, logarithmic, and interpolated curves are available separately for rise and fall
portions
Skew knob and CV control the ratio between rise and fall times without changing total envelope
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time
Envelope is triggered by Quantized trigger jack, Asynchronous trigger jack, and/or Cycle mode
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Outputs and scaling/shifting:
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Scale knob is an attenuating inverter for main envelope output (Maximum 0V to +10V non-
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inverted, and Minimum -10V to 0V inverted).
Bi-polar button centers main envelope output around 0V (-5V to +5V output)
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"+5V ENV" jack is a non-scaling output that always produces a 0V to +5V envelope, regardless
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of Scale and Bi-polar settings
"OR" jack outputs an analog OR of the two channels' scaled envelope curves. This outputs the
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highest value from either envelope at any given moment, taking into account the Scale and Bi-
polar controls.
Gate outputs:
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End-of-Rise (EOR) gate output goes high when envelope finishes a rise portion, and goes low
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when envelope begins a rise portion
End-of-Fall (EOF) gate output goes high when envelope finishes a fall portion, and goes low
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when envelope begins a fall portion
Half-R (Half-Rise) gate goes high when 50% of the time of the rise portion has elapsed, and
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goes low after 50% of the time of the fall portion (this is different than a voltage comparator-
based design). Jumper for each channel changes EOR output to a Half-Rise gate output.
Factory setting is EOR for red channel, Half-Rise for blue channel. This jack provides a 90-
degree-out-of-phase gate output useful for quadrature effects, clock phase shifting, and trigger
delay effects.
Triggering/cycling:
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Cycle button for each channel forces envelope to self-cycle (LFO mode) in sync to the ping
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clock. Button lights up when in cycle mode.
"T" jack toggles the state of both channels' Cycle buttons while a gate is applied
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"QNT" jack for each channel triggers an envelope to start at the next quantized beat, with
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respect to the divided/multiplied ping clock. Holding a gate high on this jack causes the envelope
to repeat.
"Async" jack for each channel causes an envelope to output immediately (asynchronously).
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Holding a gate high results in an AR envelope (rise-sustain-fall). If cycle mode is enabled, the
envelope will continue to cycle at this new phase with respect to the ping clock. Phase can be
reset to being in sync with the ping clock by pressing the cycle button or applying a pulse to the
QNT jack.
CV input jacks:
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CV control of each channel's Ping Div/Mult, Skew, and Curve using the CV jacks.
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Respective knobs set the center offset for the applied CV
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CV of 0-10V will modulate the parameter's full range – however, a 0-5V CV will modulate the
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parameter within a useful range.
Dimensions
20 HP Eurorack format module
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1.6" (40mm) deep
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