DG TOE10G-IP 설정 매뉴얼 - 페이지 3

{카테고리_이름} DG TOE10G-IP에 대한 설정 매뉴얼을 온라인으로 검색하거나 PDF를 다운로드하세요. DG TOE10G-IP 18 페이지. Fpga setup with cpu demo

dg_toeudp10gip_fpgasetup_intel.doc

Figure 1-1 TOE10G-IP/UDP10G-IP with CPU demo (FPGA<->PC) on Arria10 SoC

Note: Four LEDs are applied to show IP timeout status when the configuration file of the demo

uses 1-hour timeout TOE10G-IP/UDP10G-IP. After running for 1 hour, the IP stops the operation.

All LEDs are blinked to notify that the IP now is timeout. User needs to reconfigure FPGA to restart

the test.

26-Aug-20

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