DG TOE10G-IP Руководство по настройке - Страница 3
Просмотреть онлайн или скачать pdf Руководство по настройке для Материнская плата DG TOE10G-IP. DG TOE10G-IP 18 страниц. Fpga setup with cpu demo
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Figure 1-1 TOE10G-IP/UDP10G-IP with CPU demo (FPGA<->PC) on Arria10 SoC
Note: Four LEDs are applied to show IP timeout status when the configuration file of the demo
uses 1-hour timeout TOE10G-IP/UDP10G-IP. After running for 1 hour, the IP stops the operation.
All LEDs are blinked to notify that the IP now is timeout. User needs to reconfigure FPGA to restart
the test.
26-Aug-20
Page 3