DG UDP10G-IP 설정 매뉴얼 - 페이지 12

{카테고리_이름} DG UDP10G-IP에 대한 설정 매뉴얼을 온라인으로 검색하거나 PDF를 다운로드하세요. DG UDP10G-IP 18 페이지. Fpga setup with cpu demo

dg_toeudp10gip_fpgasetup_intel.doc

2 Test environment setup when using two FPGAs

Before running the test, please prepare following test environment.

• Two FPGA development boards which are the same board or different board,

Arria10 SoC/Arria10 GX/Cyclone10 GX/Stratix10 GX (H-Tile) development board

• 10Gb Ethernet cable:

a) 10 Gb SFP+ Active Optical Cable (AOC)

b) 2x10 Gb SFP+ transceiver (10G BASE-R) with optical cable (LC to LC, Multimode)

c) For Stratix10 GX board, QSFP+ to four SFP+ cable

• Two micro USB cables, one cable for connecting one FPGA board to PC

• QuartusII Programmer for programming FPGA and NiosII command shell, installed on PC

Figure 2-1 TOE10G-IP/UDP10G-IP with CPU demo (FPGA<->FPGA)

26-Aug-20

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