Chrontel CH7034B 애플리케이션 노트 - 페이지 3
{카테고리_이름} Chrontel CH7034B에 대한 애플리케이션 노트을 온라인으로 검색하거나 PDF를 다운로드하세요. Chrontel CH7034B 18 페이지. Hdtv/vga/lvds encoder
페이지 인쇄CHRONTEL
AVDD
Other
Powers
ResetB
ResetB signal is generate by system global reset. In this case, the power supply should be valid and stable for at least
20ms before the reset signal is valid. The pulse width of valid reset signal should be at least 100us. Otherwise, the
chip can't work well. The timing is shown in Figure 3.
AVDD
Other
Powers
ResetB
2.2
Internal Reference Pins
• ISET pin
206-1000-013
Rev1.4,
<9ms
Figure 2: Power-on Reset Function's Sequence on board
>20ms
Figure 3: Power-on Reset Function's Sequence on board
06/30/2020
>100
us
AN-B013
3