Chrontel CH7034B Opmerkingen over toepassingen - Pagina 3
Blader online of download pdf Opmerkingen over toepassingen voor {categorie_naam} Chrontel CH7034B. Chrontel CH7034B 18 pagina's. Hdtv/vga/lvds encoder
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AVDD
Other
Powers
ResetB
ResetB signal is generate by system global reset. In this case, the power supply should be valid and stable for at least
20ms before the reset signal is valid. The pulse width of valid reset signal should be at least 100us. Otherwise, the
chip can't work well. The timing is shown in Figure 3.
AVDD
Other
Powers
ResetB
2.2
Internal Reference Pins
• ISET pin
206-1000-013
Rev1.4,
<9ms
Figure 2: Power-on Reset Function's Sequence on board
>20ms
Figure 3: Power-on Reset Function's Sequence on board
06/30/2020
>100
us
AN-B013
3