Cypress Semiconductor CY7C1350G 사양 시트 - 페이지 4

{카테고리_이름} Cypress Semiconductor CY7C1350G에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor CY7C1350G 16 페이지. Cypress 4-mbit (128k x 36) pipelined sram with nobl architecture specification sheet

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Pin Definitions

(continued)

Name

I/O

Input-

Asynchronous

DQs

I/O-

Synchronous

DQP

I/O-

[A:D]

Synchronous

MODE

Input

Strap pin

Power Supply

I/O Power Supply Power supply for the I/O circuitry.

DDQ

Ground

Functional Overview

The CY7C1350G is a synchronous-pipelined Burst SRAM

designed specifically to eliminate wait states during

Write/Read transitions. All synchronous inputs pass through

input registers controlled by the rising edge of the clock. The

clock signal is qualified with the Clock Enable input signal

(CEN). If CEN is HIGH, the clock signal is not recognized and

all internal states are maintained. All synchronous operations

are qualified with CEN. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximum

access delay from the clock rise (t

device).

Accesses can be initiated by asserting all three Chip Enables

(CE

, CE

) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, depending on

the status of the Write Enable (WE). BW

conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Three synchronous Chip Enables (CE

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

and CE

are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory core

Document #: 38-05524 Rev. *F

ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition

with data integrity preserved.During normal operation, this pin has to be low or left floating. ZZ pin

has an internal pull-down.

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the address during the clock rise of the read cycle. The direction of the pins is

controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as

outputs. When HIGH, DQ

and DQP

cally tri-stated during the data portion of a write sequence, during the first clock when emerging from

a deselected state, and when the device is deselected, regardless of the state of OE.

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ

sequences, DQP

is controlled by BW

[A:D]

Mode Input. Selects the burst order of the device. When tied to GND selects linear burst

sequence. When tied to VDD or left floating selects interleaved burst sequence.

Power supply inputs to the core of the device.

Ground for the device.

No Connects. Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are

address expansion pins in this device and will be used as address pins in their respective densities.

) is 2.6 ns (250-MHz

can be used to

[A:D]

, CE

) and an

, CE

Description

are placed in a tri-state condition. The outputs are automati-

correspondingly.

[A:D]

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus, provided OE

is active LOW. After the first clock of the read access the output

buffers are controlled by OE and the internal control logic. OE

must be driven LOW in order for the device to drive out the

requested data. During the second clock, a subsequent

operation (Read/Write/Deselect) can be initiated. Deselecting

the device is also pipelined. Therefore, when the SRAM is

deselected at clock rise by one of the chip enable signals, its

output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1350G has an on-chip burst counter that allows the

user the ability to supply a single address and conduct up to

four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address into the

SRAM, as described in the Single Read Access section above.

The sequence of the burst counter is determined by the MODE

input signal. A LOW input on MODE selects a linear burst

mode, a HIGH selects an interleaved burst sequence. Both

burst counters use A0 and A1 in the burst sequence, and will

wrap around when incremented sufficiently. A HIGH input on

ADV/LD will increment the internal burst counter regardless of

the state of chip enables inputs or WE. WE is latched at the

beginning of a burst cycle. Therefore, the type of access (Read

or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

and CE

are ALL asserted active, and (3) the Write signal WE

is asserted LOW. The address presented to the address inputs

is loaded into the Address Register. The write signals are

latched into the Control Logic block.

CY7C1350G

. During write

, CE

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