EG&G ORTEC 552 운영 및 서비스 매뉴얼 - 페이지 13

{카테고리_이름} EG&G ORTEC 552에 대한 운영 및 서비스 매뉴얼을 온라인으로 검색하거나 PDF를 다운로드하세요. EG&G ORTEC 552 16 페이지. Pulse-shape analyzer and timing single-channel analyzer

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from IC8-15 triggers a current switch to generate a NIM-

standard fast negative output pulse through CN3 on the

front panel.

5.9.

CHANNEL B DISCRIMINATOR

The channel B discriminator Is 109. The Input signal Is

furnished through pin 3 and the reference level Is fur

nished through pin 4. At the onset of the Input pulse, the

level at pin 3 rises faster than the level at pin 4 and this sets

the discriminator with a low at pin 9 and a high at pin 11.

The level at pin 4 Is furnished from the peak stretcher so

It will remain at a fixed level, which Is an amplitude pro

portional to the Input peak, while the Input pulse decays.

When the Input pulse decay crosses the reference level,

109 Is reset to generate the channel B trigger. Switch 34

on the front panel selects the fractional level that Is effec

tive for the pin 4 reference level; this level can be set at 10%

through 90%, In 10% Increments, or at Bl (equivalent to

100%), where each fraction Is measured down from the

peak amplitude.

When 109 Is reset, the level at Its pin 11 goes to ground

to Indicate recognition of the constant-fraction point on

the decay of the Input pulse. This output Is furnished to

an EOL gate, Q27B through Q47. This serves as both the

SOA logic gate and the constant-fraction trigger gate, and

must be enabled from 105-11 In order to respond to the

OF trigger. With the logic satisfied, the trigger forces the

collector of Q41 high and It will remain high until It Is reset.

The high transition at Q410 Is furnished through the delay

circuitry that Includes Q28, Q29, Q42, Q33, Q32, Q30, and

Q31. The Input pair, Q28 and Q29, Is biased from Q290

and Q29D operating as a temperature compensated cur

rent source. Normally 028 Is off and its collector Is In the

high state. At the Input pulse, 028 turns on and 029 turns

off. The low transition at the collector of 028 Is fed

through O30 to storage capacitor 076. Thus the 029 base

voltage Is stepped In a negative direction through 076.

Oapacltor 076 Is charged by temperature compensated

source 032 and 033, and the rate Is determined (for In

ternal strobe operation) by front panel Delay control

R189. When the storage capacitor has charged back to

the point where the base of 029 Is at the same level as the

base of 028, 029 turns on again to switch the collector of

029 to the low state. When the collector of 029 switches

to the low state, an output for channel B will be generated.

For internal strobe operation, 1010-15 Is enabled by +5 V

through D17. When 0290 goes high at the trigger Input,

IC10-15 Is high and IC10-9 Is low, so IC10-3 Is low. At the

end of the delay, when 0290 goes low, this switches

IO10-9 to high and IO10-15 to low. For 10 ns, both Inputs

to 1010-3 are high so there Is a 10-ns positive pulse gen

erated at 1010-3. This pulse triggers output generator

046, 045, 036, 037, and 038 through 066 to furnish a

NlM-standard slow positive pulse through 0N7 on the

rear panel and 0N8 on the front panel. The 1010-3 output

Is also Inverted through 044 to trigger the current switch

that generates the NlM-standard fast negative output

through 0N9.

For external strobe operation, the charge circuit for 076

Is through R188, so 029 Is turned on after 10

If It has not

already been turned on by an external strobe pulse. While

029 Is turned off, gate IO10-15 Is enabled at Its pin 13and

will trigger an output pulse If a NlM-standard slow posi

tive pulse Is furnished through 0N3 on the rear panel. The

strobe Input Is coupled through 025 and 026 to start the

output pulse generation through 1010-15 In the same

manner as described for Internal strobe operation. At the

leading edge of the strobe Input, the signal through 033

and 034 will quickly charge 076 and turn off 029 to reset

the system. If 029 Is turned on by 076 before a strobe Is

furnished, gate IO10-15 will be disabled so that the strobe

will have no effect.

5.10.

RESET CIRCUIT

An Internal reset Is generated at 106-12 when all three

Inputs are high. The Input at pin 2 goes high when both

channel A and channel B discriminators are reset (the

trigger point). The Input at pin 13 goes high when the

lower-level discriminator Is reset by having the Input

pulse amplitude fall back through the reference level.

The 104-3 level stays high, latched, until the flip flop Is

reset, so the Input to pin 1 of 106-12 Is also high. Thus,

after all three events have taken place (lower-level dis

criminator reset and both channels triggered) the Inputs

to 106-12 are all high to generate reset. The reset signal

Is furnished to 104-6 and 104-8 to reset both discriminator

latches and to the Input stretcher circuit to discharge

Its stretched peak level.

5.11.

DC POWER

Input power from the bin and power supply Is accepted

through the module connector on the rear panel. The 552

operates on 166 mA through the +12 V circuit, 166 mA

through tne -12 V circuit, 83 mA from +24 V, and 83 mA

from -24 V.

Internally the +12-V source Is used to generate a regu

lated +5 V by 1011 and -12 V Is used to generate a reg

ulated -5 V by 1012.