Chrontel CH7515A Layout Design Manual - Page 2

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CHRONTEL
Table 1: Power Supply Pins Assignment of the CH7515A (128TQFP)
Pin Assignment
3, 5, 112
4, 111
8, 85
9, 86
21, 47, 74
22, 48, 73
101
97
113, 119, 125
116, 122
126
128
VCC1_8
47R 100MHz
L1
1
2
VDDPLL
C1
10uF
47R 100MHz
L2
1
2
DVDD
VCC3_3
47R 100MHz
L3
1
2
AVDD
C13
10uF
Note:
Pease make sure the Voltage of AVCC and AVDD (VCC33) should be given earlier than the DVDD
1.
and VDDPLL (VCC18).
The RB signal should be given to CH7515A after the powers are stable.
2.
2
# Of Pins
Type
3
Power
2
Ground
2
Power
2
Ground
3
Power
3
Ground
1
Power
1
Ground
3
Power
2
Ground
1
Power
1
Ground
U1
3, 5, 112
VDDPLL
C2
C3
C4
4, 111
0.1uF
0.1uF
0.1uF
GNDPLL
8, 85
DVDD
C7
C8
C9
9, 86
10uF
0.1uF
0.1uF
DGND
21, 47, 74
AVDD
C19
C14
C15
22, 48, 73
0.1uF
0.1uF
0.1uF
AGND
CH7515A
CH7515A
T1
VCC33
VCC18
RB
Figure 1: Power Supply Decoupling and Distribution
Symbol
Description
VDDPLL
PLL Power Supply (1.8V)
GNDPLL
PLL Ground
DVDD
Digital Power Supply (1.8V)
DGND
Digital Power Ground
AVDD
LVDS Power Supply (3.3V)
AGND
LVDS Ground
AVCC
Analog Power Supply (3.3V)
AVSS
Analog Ground
VDDRX
DP Rx Power Supply (1.8V)
GNDRX
DP Rx Ground
VDDBG
Band-gap Power Supply (1.8V)
GNDBG
Band-gap Ground
101
AVCC
97
AVSS
113, 119, 125
VDDRX
TQFP
116, 122
GNDRX
126
VDDBG
128
GNDBG
206-1000-021
AN-B021
VCC3_3
47R 100MHz
L4
1
2
AVCC
C6
C5
0.1uF
10uF
VCC1_8
47R 100MHz
L5
1
2
VDDRX
C12
C10
C11
0.1uF
0.1uF
10uF
47R 100MHz
L6
1
2
VDDBG
C18
C16
C17
0.1uF
0.1uF
10uF
Rev 1.0
2020-07-15