Cypress Semiconductor CY7C1223H Specification Sheet - Page 6

Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1223H. Cypress Semiconductor CY7C1223H 17 pages. Cypress 2-mbit (128k x 18) pipelined dcd sync sram specification sheet

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Interleaved Burst Address Table (MODE = Floating or V
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
00
10
11
11
10
[2, 3, 4, 5, 6]

Truth Table

Operation
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
ZZ Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
2. X = "Don't Care." H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW
BWE , GW=H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05674 Rev. *B
)
DD
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
10
00
01
01
00
Address
Used
CE
CE
CE
ZZ ADSP ADSC
1
2
3
None
H
X
X
L
None
L
L
X
L
None
L
X
H
L
None
L
L
X
L
None
L
X
H
L
None
X
X
X
H
External
L
H
L
L
External
L
H
L
L
External
L
H
L
L
External
L
H
L
L
External
L
H
L
L
Next
X
X
X
L
Next
X
X
X
L
Next
H
X
X
L
Next
H
X
X
L
Next
X
X
X
L
Next
H
X
X
L
Current
X
X
X
L
Current
X
X
X
L
Current
H
X
X
L
Current
H
X
X
L
Current
X
X
X
L
Current
H
X
X
L
, BW
) and BWE = L or GW = L. WRITE = H when all Byte write enable signals ( BW
A
B
Linear Burst Address Table (MODE = GND)
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
10
10
11
11
00
ADV
WRITE
X
L
X
X
L
X
X
X
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
L
X
X
X
L
X
X
X
H
L
X
L
H
L
X
H
H
L
X
H
H
H
L
H
H
H
L
H
X
H
L
H
X
H
L
H
H
H
L
L
X
H
L
L
H
H
H
H
H
H
H
H
X
H
H
H
X
H
H
H
H
H
H
L
X
H
H
L
. Writes may occur only on subsequent clocks
[A:B]
CY7C1223H
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
00
00
01
01
10
OE
CLK
DQ
X
L-H
Tri-State
X
L-H
Tri-State
X
L-H
Tri-State
X
L-H
Tri-State
X
L-H
Tri-State
X
X
Tri-State
L
L-H
Q
H
L-H
Tri-State
X
L-H
D
L
L-H
Q
H
L-H
Tri-State
L
L-H
Q
H
L-H
Tri-State
L
L-H
Q
H
L-H
Tri-State
X
L-H
D
X
L-H
D
L
L-H
Q
H
L-H
Tri-State
L
L-H
Q
H
L-H
Tri-State
X
L-H
D
X
L-H
D
, BW
),
A
B
Page 6 of 16
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