Cypress Semiconductor CY7C1334H Specification Sheet - Page 11
Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1334H. Cypress Semiconductor CY7C1334H 14 pages. 2-mbit (64k x 32) pipelined sram with nobl architecture
Print PageSwitching Waveforms
NOP, STALL, and Deselect Cycles
1
CLK
CEN
CE
ADV/LD
WE
BW
[A:D]
A1
ADDRESS
Data
In-Out (DQ)
WRITE
D(A1)
[22, 23]
ZZ Mode Timing
CLK
ZZ
I
SUPPLY
ALL INPUTS
(except ZZ)
Outputs (Q)
Notes:
21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
22. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
23. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05678 Rev. *B
(continued)
[18, 19, 21]
2
3
4
A2
A3
D(A1)
READ
STALL
READ
Q(A2)
Q(A3)
DON'T CARE
t
ZZ
t ZZI
I DDZZ
5
6
7
A4
Q(A2)
Q(A3)
WRITE
STALL
NOP
D(A4)
UNDEFINED
High-Z
DON'T CARE
CY7C1334H
8
9
10
A5
t
CHZ
D(A4)
Q(A5)
READ
DESELECT
CONTINUE
Q(A5)
DESELECT
t ZZREC
t RZZI
DESELECT or READ Only
Page 11 of 13
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