Cypress Semiconductor CY7C1339G Specification Sheet - Page 10
Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1339G. Cypress Semiconductor CY7C1339G 18 pages. Cypress 4-mbit (128k x 32) pipelined sync sram specification sheet
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Switching Characteristics
Parameter
t
V
(Typical) to the first Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid After CLK Rise
CO
t
Data Output Hold After CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
t
OE LOW to Output Valid
OEV
t
OE LOW to Output Low-Z
OELZ
t
OE HIGH to Output High-Z
OEHZ
Set-up Times
t
Address Set-up Before CLK Rise
AS
t
ADSC, ADSP Set-up Before CLK Rise
ADS
t
ADV Set-up Before CLK Rise
ADVS
t
GW, BWE, BW
WES
t
Data Input Set-up Before CLK Rise
DS
t
Chip Enable Set-Up Before CLK Rise
CES
Hold Times
t
Address Hold After CLK Rise
AH
t
ADSP, ADSC Hold After CLK Rise
ADH
t
ADV Hold After CLK Rise
ADVH
t
GW, BWE, BW
WEH
t
Data Input Hold After CLK Rise
DH
t
Chip Enable Hold After CLK Rise
CEH
Notes:
12. This part has a voltage regulator internally; t
can be initiated.
13. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
14. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
16. Timing reference level is 1.5V when V
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05520 Rev. *F
[12, 13, 14, 15, 16, 17]
Over the Operating Range
Description
[12]
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
Set-up Before CLK Rise
X
Hold After CLK Rise
X
is the time that the power needs to be supplied above V
POWER
is less than t
and t
is less than t
OEHZ
OELZ
CHZ
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
–250
–200
Min.
Max.
Min.
Max.
1
1
4.0
5.0
1.7
2.0
1.7
2.0
2.6
2.8
1.0
1.0
0
0
2.6
2.8
2.6
2.8
0
0
2.6
2.8
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
(minimum) initially before a read or write operation
DD
to eliminate bus contention between SRAMs when sharing the same
CLZ
CY7C1339G
–166
–133
Min.
Max. Min. Max.
Unit
1
1
ms
6.0
7.5
2.5
3.0
2.5
3.0
3.5
4.0
1.5
1.5
0
0
3.5
4.0
3.5
4.0
0
0
3.5
4.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Page 10 of 18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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