Chrontel CH7219 Toepassingsnotitie - Pagina 3

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CHRONTEL

2.2

Internal Reference Pins

• RBIAS pin

This pin sets the reference current for internal circuit. A 1 KΩ, 1% tolerance resistor should be connected between

RBIAS and GND as shown in Figure 3. The distance between the resistor and the CH7219 should be less than 6mm,

the shorter and wider trace the better. For optimal performance, this signal should not overlay the analog power or

analog output signals.

2.3

General Control Pins

• RB

This pin is the chip reset pin for the CH7219. The RB pin is internally pulled-up. But when it is pulled-low, this pin

places the device in the power-on-reset condition.

The RB signal can be generated by on board Resistor and Capacitor delay, as shown in Figure 5, one 1MΩ resistor is

necessary to be pulled high to 3.3V. One 0.1uf capacitor is recommended to be pulled low to GND. After the powers

are stable, RB signal (low to high) is generated and sent to the chip, as shown in Figure 2.

While RB signal is generated by system global reset. In this case, the power supply should be valid and stable for at

least 20ms before the reset signal is valid. The pulse width of valid reset signal should be at least 100us. Otherwise,

the chip can't work well. The timing is shown in Figure 4.

Figure 4: Power-on Reset Function's Sequence external global reset

Note:

The rising threshold of RB is 2.4V.

The falling threshold of RB is 0.4V.

• XI, XO

A 25MHz crystal (30ppm) can be connected to XI and XO as the CH7219 the optional reference clock input. In

PCB design, a 25MHz crystal must be placed as close as possible to the XI and XO pins, with traces connected from

206-1000-058

Rev. 0.1

RBIAS

QFN

CH7219

Figure 3: RBIAS Pin Connection

3.3V

>20ms

1.2V

ResetB

2023-10-25

R1 1K(1%)

>100

AN-B058