Chrontel CH7219 Toepassingsnotitie - Pagina 4
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point to point, overlaying the ground plane. Since the crystal generates the timing reference for the CH7219, it is
essential that noise not couple into these input pins.
The crystal load capacitance, CL, is usually specified in the crystal spec from the vendor. Refer to Figure 5 for a
crystal circuit reference design and an example of load capacitors.
• GPIO0~8
General Purpose Input/Output Interface
2.4
Serial Port Control Pins
• SPC0 and SPD0
SPD0 and SPC0 function as a serial interface where SPD0 is the bi-directional data and SPC0 is an input-only serial
clock. In the reference design, SPD0 and SPC0 pins are pulled up to +3.3V with 6.8k resistors. Through these two
pins, the internal register values of the chip can be read.
• DDC_SC and DDC_SD
DDC_SC and DDC_SD are used to interface with the DDC of DVI/HDMI receiver. This DDC pair needs to be pulled
up to 5V through 1.8 KΩ resistors
4
22pF
Y 1
U1
25MHz
3
XI/CK_25M
4
XO
22pF
13
RB
CH7219
Figure 5: General Control Pins
VDD5
D15
SM5817
R2
R1
U1
1.8K
1.8K
51
DDC_SCL_HDMI
DDC_SCL
50
DDC_SDA_HDMI
DDC_SDA
CH7219
45
SPC0
44
QFN
SPD0
Figure 6: Serial Port Interface
C2
VCC3_3
C3
R1
1M
C1
0.1uF
VCC3_3
R3
R4
6.8K
6.8K
206-1000-058
AN-B058
Rev. 0.1
2023-10-25