Cypress Semiconductor CY25819 Specificatieblad - Pagina 3
Blader online of download pdf Specificatieblad voor {categorie_naam} Cypress Semiconductor CY25819. Cypress Semiconductor CY25819 7 pagina's. Cypress spread spectrum clock generator specification sheet
Pagina afdrukken3-Level Digital Inputs
S0 digital input is designed to sense three logic levels desig-
nated as HIGH "1," LOW "0," and MIDDLE "M." With this
3-Level digital input logic, the 3-Level logic is able to detect
three different logic levels.
The S0 pin includes an on-chip 20K (10K/10K) resistor divider.
No external application resistors are needed to implement
3-Level logic, as follows.
Logic Level "0": 3-Level logic pin connected to GND.
Logic Level "M": 3-Level logic pin left floating (no connection.)
Logic Level "1": 3-Level logic pin connected to Vdd.
Figure 1 illustrates how to implement 3-Level Logic.
L O G IC
L O G IC
L O W (0 )
M ID D L E (M )
S 0
S 0
U N C O N N E C T E D
to V S S
V S S
Figure 1. 3-Level Logic
Table 3. Modulation Rate Divider Ratios
Product
CY25818
CY25819
[1, 2]
Maximum Ratings
Supply Voltage (Vdd): ..................................................+ 5.5V
Input Voltage Relative to Vdd:.............................. Vdd + 0.3V
Table 4. DC Electrical Characteristics Vdd = 3.3V ±10%, T
Parameter
Description
Vdd
Power Supply Range
V
Input HIGH Voltage
INH
V
Input MIDDLE Voltage
INM
V
Input LOW Voltage
INL
V
Output HIGH Voltage
OH1
V
Output HIGH Voltage
OH2
V
Output LOW Voltage
OL1
V
Output LOW Voltage
OL2
C
Input Capacitance
IN1
C
Input Capacitance
IN2
I
Power Supply Current
DD1
I
Power Supply Current
DD3
I
Power Supply Current
DD4
Document #: 38-07362 Rev. *B
Modulation Rate
Spread Spectrum Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (fmax) and
minimum frequency of the clock (fmin) determine this band of
frequencies. The time required to transition from fmin to fmax
and back to fmin is the period of the Modulation Rate, Tmod.
The Modulation Rates of SSCG clocks are generally referred
to in terms of frequency, and fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider
determine the Modulation Rate.
In the case of CY25818/19 devices, the (Spread Spectrum)
Modulation Rate, fmod, is given by the following formula:
L O G IC
fmod = f
H IG H (H )
where fmod is the Modulation Rate, f
and DR is the Divider Ratio, as given in Table 3.
V D D
S 0
to V D D
Input Frequency Range
8–16 MHz
16–32 MHz
Input Voltage Relative to Vss:............................... Vss + 0.3V
Operating Temperature:................................... 0°C to + 70°C
Storage Temperature: ................................ –65°C to + 150°C
= 0°C to +70°C and C
A
Conditions
S0 Input
S0 Input
S0 Input
I
= 4 ma, SSCLK and REFCLK
OH
I
= 6 ma, SSCLK and REFCLK
OH
I
= 4 ma, SSCLK Output
OL
I
= 10 ma, SSCLK Output
OL
X
(Pin 1) and X
(Pin 8)
IN
OUT
All Digital Inputs
F
=8 MHz, no load
IN
F
=32 MHz, no load
IN
PD# = Vss
/DR
IN
IN
Divider Ratio (DR)
256
512
= 15 pF (unless otherwise noted)
L
Min.
Typ.
2.97
3.3
0.85 Vdd
Vdd
0.40 Vdd
0.50 Vdd
0.0
0.0
2.4
–
2.0
–
–
–
–
–
6.0
7.5
3.5
4.5
–
10.0
–
19.0
–
150
CY25818/19
is the Input Frequency,
Max.
Unit
3.63
V
Vdd
V
0.60 Vdd
V
0.15 Vdd
V
–
V
–
V
0.4
V
1.2
V
9.0
pF
6.0
pF
12.5
mA
23.0
mA
250
mA
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