Cypress Semiconductor STK14C88-5 Specificatieblad - Pagina 10
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SRAM Write Cycle
Parameter
Cypress
Alt
Parameter
t
t
WC
AVAV
t
t
t
PWE
WLWH,
WLEH
t
t
t
SCE
ELWH,
ELEH
t
t
t
SD
DVWH,
DVEH
t
t
t
HD
WHDX,
EHDX
t
t
t
AW
AVWH,
AVEH
t
t
t
SA
AVWL,
AVEL
t
t
t
HA
WHAX,
EHAX
[11,12]
t
t
WLQZ
HZWE
[11]
t
t
WHQX
LZWE
Switching Waveforms
ADDRESS
CE
WE
DATA IN
DATA OUT
ADDRESS
CE
WE
DATA IN
DATA OUT
Notes
12. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
13. HSB must be high during SRAM WRITE cycles.
14. CE or WE must be greater than V
Document Number: 001-51038 Rev. **
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
Figure 10. SRAM Write Cycle 1: WE Controlled
t
SA
PREVIOUS DATA
Figure 11. SRAM Write Cycle 2: CE Controlled
t
SA
t
AW
t
HIGH IMPEDANCE
during address transitions.
IH
35 ns
Min
Max
35
25
25
12
0
25
0
0
13
5
t
WC
t
SCE
t
AW
t
PWE
t
SD
DATA VALID
t
HZWE
HIGH IMPEDANCE
[13, 14]
t
WC
t
SCE
PWE
t
SD
DATA VALID
STK14C88-5
45 ns
Min
Max
45
30
30
15
0
30
0
0
15
5
[13, 14]
t
HA
t
HD
t
LZWE
t
HA
t
HD
Page 10 of 17
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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