Digilent Pmod CMPS2 Podręcznik referencyjny - Strona 9

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Pmod CMPS2™ Reference Manual

I2CBegin(0xA1); //device ID 0x30 with a read (1) bit

32. Wait to receive an ACK from the Pmod CMPS2.

33. Cycle the SCL line to receive the data bits from the X, Y, and Z registers in the SDA line, providing an ACK

between each data byte. The Pmod CMPS2 address pointer automatically moves to each consecutive

byte. End the communication by sending a NACK followed by a STOP command.

I2CReadMultiple(6); //read six bytes, sending an ACK to the slave device betwe

en each byte received and a NACK after the last byte

34. Each of the readings will contain the external magnetic field H in addition to offset associated with the

current put through the coil by the SET action.

35. Now a RESET action will be performed to reverse the magnetization for the sensing resistors to get the

inverse offset value.

36. Provide a START condition and call the device ID with a write bit

I2CBegin(0xA0); //device ID 0x30 with a write (0) bit

37. Wait to receive an ACK from the Pmod CMPS2.

38. Send the Internal Control Register 0 (address 0x07) as the register to communicate with

I2CWrite(0x07); //address 0x07 corresponds to Control Register 0

39. Wait to receive an ACK from the Pmod CMPS2.

40. Write the command to recharge the capacitor to prepare for the RESET action.

I2CWrite(0x80); //0x80 refills the capacitor

41. Wait to receive an ACK from the Pmod CMPS2.

42. Delay at least 50 mS to allow the Pmod CMPS2 to finish preparing.

43. Provide a START condition and call the device ID with a write bit

I2CBegin(0xA0); //device ID 0x30 with a write (0) bit

44. Wait to receive an ACK from the Pmod CMPS2.

45. Send the Internal Control Register 0 (address 0x07) as the register to communicate with

I2CWrite(0x07); //address 0x07 corresponds to Control Register 0

46. Wait to receive an ACK from the Pmod CMPS2.

47. Write the command to start a RESET action.

I2CWrite(0x40); //0x40 starts the RESET action

48. Wait to receive an ACK from the Pmod CMPS2.

49. Delay at least 1 mS to allow the Pmod CMPS2 to finish the SET action.

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